Computer arithmetic algorithms
Computer arithmetic algorithms
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
On the Construction of Optimal Time Adders (Extended Abstract)
STACS '88 Proceedings of the 5th Annual Symposium on Theoretical Aspects of Computer Science
Correction to "A Fast Binary Adder with Conditional Carry Generation"
IEEE Transactions on Computers
Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator
Analog Integrated Circuits and Signal Processing
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This brief contribution presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 驴m static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.