A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Diminished-One Modulo 2^n +1 Adder Design
IEEE Transactions on Computers
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Modulo 2n ± 1 Adder Design Using Select-Prefix Blocks
IEEE Transactions on Computers
A Full RNS Implementation of RSA
IEEE Transactions on Computers
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Efficient modulo 2n+1 adder architectures
Integration, the VLSI Journal
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
On the Design of Modulo 2^n+1 Multipliers
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
IEEE Transactions on Computers
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Efficient Modulo $2^{n}+1$ Multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work a new efficient modulo 2^n+1 modified Booth multiplication algorithm for both operands in the weighted representation is proposed. Furthermore, the same algorithm is extended to realize modulo 2^n+1 multiply-add units. The derived partial products are reduced by an inverted end around carry-save adder tree to two operands, which are finally added by a modulo 2^n+1 adder. The performance and efficiency of the proposed multipliers are evaluated and compared against the earlier modulo 2^n+1 multipliers, based on a single gate level model. Comparisons based on experimental CMOS implementations for both the multiply and multiply-add units are also given. The proposed multipliers yield area and power savings by an average of 15% and 10% respectively, while the corresponding area and power savings of the proposed multiply-add units are 14% and 21% respectively.