Network and internetwork security: principles and practice
Network and internetwork security: principles and practice
Instruction set selection for ASIP design
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
An ASIP design methodology for embedded systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Computers
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
Architectural support for fast symmetric-key cryptography
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
CryptoManiac: a fast flexible architecture for secure communication
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System design methodologies for a wireless security processing platform
Proceedings of the 39th annual Design Automation Conference
Handbook of Applied Cryptography
Handbook of Applied Cryptography
The Design of Rijndael
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
The Garp Architecture and C Compiler
Computer
A Reduced-Area Scheme for Carry-Select Adders
IEEE Transactions on Computers
Proceedings of the Third International Workshop on Fast Software Encryption
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
New Block Encryption Algorithm MISTY
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Rijndael FPGA Implementations Utilising Look-Up Tables
Journal of VLSI Signal Processing Systems
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards
SBAC-PAD '02 Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing
Modeling and mapping for dynamically reconfigurable hybrid architectures
Modeling and mapping for dynamically reconfigurable hybrid architectures
Reconfigurable computing for symmetric-key algorithms
Reconfigurable computing for symmetric-key algorithms
Hardware Implementation of the Binary Method for Exponentiation in GF(2m)
ENC '03 Proceedings of the 4th Mexican International Conference on Computer Science
AES Algorithm Implementation-An efficient approach for Sequential and Pipeline Architectures
ENC '03 Proceedings of the 4th Mexican International Conference on Computer Science
AES and the cryptonite crypto processor
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Telekom's MAGENTA algorithm for en-/decryption in the Gigabit/sec range
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
An instruction set extension for fast and memory-efficient AES implementation
CMS'05 Proceedings of the 9th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Algorithm and architecture for a Galois field multiplicative arithmetic processor
IEEE Transactions on Information Theory
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Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers, including the Advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microprocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC V8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication.