Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
An 8-bit systolic AES architecture for moderate data rate applications
Microprocessors & Microsystems
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
| Hi-index | 0.00 |
We present an efficient implementation of Rijndaelcryptographic algorithm on FPGAs, new AdvanceEncryption Standard (AES). The implementation of AEShas been made both in sequential and pipelinearchitectures and we are able to compare the results asan area time trade-off. In sequential architecture, thedesign occupies 2744 CLB slices and achieved athroughput of 258.5 Mbits/s and there is no use of extramemory resources like FPGA BRAMs. On the otherhand, our pipeline design occupies a total of 2136 CLBslices and achieved a throughput of 2868 Mbits/s. Bothdesigns were realized on VirtexE family of devices(XCV812). The performance figures achieved by ourimplementations are not only efficient in terms ofthroughput but also area occupied by them are amongthe most economical reported up-to-date.