Computer
VIS Speeds New Media Processing
IEEE Micro
Subword Parallelism with MAX-2
IEEE Micro
Securing wireless data: system architecture challenges
Proceedings of the 15th international symposium on System Synthesis
Microarchitectural denial of service: insuring microarchitectural fairness
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Emerging challenges in designing secure mobile appliances
Ambient intelligence
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Security in embedded systems: Design challenges
ACM Transactions on Embedded Computing Systems (TECS)
Securing Mobile Appliances: New Challenges for the System Designer
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Design Methodology for Efficient Application-Specific On-Chip Interconnects
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 43rd annual Design Automation Conference
Hybrid architectures for efficient and secure face authentication in embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sorter based permutation units for media-enhanced microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable solutions for very-long arithmetic with applications in cryptography
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Integrated Computer-Aided Engineering - Artificial Neural Networks
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Efficient software architecture for IPSec acceleration using a programmable security processor
Proceedings of the conference on Design, automation and test in Europe
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Journal of Signal Processing Systems
Security analysis of the full-round DDO-64 block cipher
Journal of Systems and Software
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An architecture-independent instruction shuffler to protect against side-channel attacks
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
An instruction set extension for fast and memory-efficient AES implementation
CMS'05 Proceedings of the 9th IFIP TC-6 TC-11 international conference on Communications and Multimedia Security
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
| Hi-index | 0.00 |
Performing permutations in software can facilitate more widespread use of secure information processing and faster multimedia processing. But current instruction set architectures, even when augmented with subword-parallel multimedia instructions, do not provide efficient, bit-level software permutations. Four new instructions each offer a solution.