Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Symbiotic jobscheduling for a simultaneous multithreaded processor
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CryptoManiac: a fast flexible architecture for secure communication
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Symbiotic jobscheduling with priorities for a simultaneous multithreading processor
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The optimum pipeline depth for a microprocessor
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Increasing processor performance by implementing deeper pipelines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
IEEE Micro
Evaluating the impact of simultaneous multithreading on network servers using real hardware
SIGMETRICS '05 Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Memory performance attacks: denial of memory service in multi-core systems
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Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date, most research investigating the scheduling of these shared resources has focused on enhancing computational bandwidth. In this paper, we examine scheduling fairness. First, we show that a thread running on an implementation of a SMT processor can suffer from "denial of service" by a malicious thread, slowing down the original thread by a factor of 10--20. Using performance counter hardware, we show that the slowdown occurs because of deliberate misuse of shared resources and design decisions that are necessary for high speed implementation.We then propose and evaluate a number of mechanisms to counter such malicious behavior: some affect the core scheduling algorithm and others simply attempt to identify activity that would affect threads sharing the same processor core. We find that harmful activity based mechanisms outperform core scheduling mechanisms. In addition, we show that they can be designed so that they can differentiate between malicious attacks and legitimate activities that may also make use of the same harmful activities.