Column-associative caches: a technique for reducing the miss rate of direct-mapped caches
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Microarchitectural denial of service: insuring microarchitectural fairness
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
A scheduling model for reduced CPU energy
FOCS '95 Proceedings of the 36th Annual Symposium on Foundations of Computer Science
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Soft Real- Time Scheduling on Simultaneous Multithreaded Processors
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
IEEE Transactions on Parallel and Distributed Systems
Power-Aware Scheduling for Periodic Real-Time Tasks
IEEE Transactions on Computers
Profile-based optimal intra-task voltage scheduling for hard real-time applications
Proceedings of the 41st annual Design Automation Conference
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
On the Limits of Leakage Power Reduction in Caches
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
WCRT analysis for a uniprocessor with a unified prioritized cache
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Architectural support for real-time task scheduling in SMT processors
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Optimizing intra-task voltage scheduling using data flow analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Predictable Performance in SMT Processors: Synergy between the OS and SMTs
IEEE Transactions on Computers
Scope-Aware Data Cache Analysis for WCET Estimation
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
Dynamic voltage scaling of mixed task sets in priority-driven systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Simultaneous multithreading (SMT) and chip-multiprocessor (CMP) are currently two important trends in the design of processors. As the processor executes more than two programs simultaneously, these programs will compete keenly for the use of the cache. This makes it more difficult to predict the worst case computation time (WCET), and might even lead to an overall low efficiency in certain circumstances. Even though the traditional cache partitioning method can solve the foregoing two problems, it reduces the utility rate of the cache as well as the performance of the processor. The method presented in this paper allows the processors to share the cache without affecting each other. It makes the WCET analysis more easily on a multithreaded CPU architecture (e.g., SMT and CMP). Furthermore, the idea of the cache design is based on a power-efficient (i.e., environment friendly) design called ``drowsy cache'' and the power-efficiency feature is inherited.