Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
MIPS: A microprocessor architecture
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Register allocation across procedure and module boundaries
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Performance evaluation of a commercial cache-coherent shared memory multiprocessor
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
The effects of virtually addressed caches on virtual memory design and performance
ACM SIGOPS Operating Systems Review
A graphical comparison of RISC processors
ACM SIGARCH Computer Architecture News
Consistency management for virtually indexed caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Architecture support for single address space operating systems
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Architectural support for translation table management in large address space machines
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The expected lifetime of “single-address-space” operating systems
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Hardware support for fast capability-based addressing
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Sharing and protection in a single-address-space operating system
ACM Transactions on Computer Systems (TOCS) - Special issue on computer architecture
Virtual address translation for wide-address architectures
ACM SIGOPS Operating Systems Review
A new page table for 64-bit address spaces
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
Functional Implementation Techniques for CPU Cache Memories
IEEE Transactions on Computers - Special issue on cache memory and related problems
Concurrent Event Handling through Multithreading
IEEE Transactions on Computers
The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Subword Parallelism with MAX-2
IEEE Micro
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
IEEE Transactions on Computers
Efficient Stack Simulation for Set-Associative Virtual Address Caches With Real Tags
IEEE Transactions on Computers
PA7300LC Integrates Cache for Cost/Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Locking with Different Granularities for Reads and Writes in an MVM System
IDEAS '99 Proceedings of the 1999 International Symposium on Database Engineering & Applications
Architectural techniques for accelerating subword permutations with repetitions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Implementation of multiple pagesize support in HP-UX
ATEC '98 Proceedings of the annual conference on USENIX Annual Technical Conference
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Journal of Signal Processing Systems
Multi-view memory to support OS locking for transaction systems
IDEAS'97 Proceedings of the 1997 international conference on International database engineering and applications symposium
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The processor component of the Hewlett-Packard Precision Architecture system is described. The architecture's goals, how the architecture addresses the spectrum of general-purpose user information processing needs, and some architectural design tradeoffs are examined. Extendibility and longevity features are considered.