Hardware support for fast capability-based addressing

  • Authors:

  • Nicholas P. Carter;Stephen W. Keckler;William J. Dally

  • Affiliations:

  • Artificial Intelligence Laboratory, Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA;Artificial Intelligence Laboratory, Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA;Artificial Intelligence Laboratory, Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, Cambridge, MA

  • Venue:
  • ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
  • Year:
  • 1994

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Abstract

Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to record access permissions for processes. With the advent of computers that supported cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments.This paper examines guarded pointers, a hardware technique which uses tagged 64-bit pointer objects to implement capability-based addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one level of address translation is required to perform a memory reference. Sharing data between processes is efficient, and protection states are defined to allow fast protected subsystem calls and create unforgeable data keys.