MOOSS2: a CPU with support for HLL memory structures

Authors:
Radim Ballner;Pavel Tvrdik
Affiliations:
Department of Computer Science and Engineering, Faculty of Electrical Engineering, Czech Technical University, Czech Republic;Department of Computer Science and Engineering, Faculty of Electrical Engineering, Czech Technical University, Czech Republic
Venue:
ACST'07 Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology
Year:
2007

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Abstract

A support for high level programming languages (HLLs) and operating systems was addressed by many researches for decades. This support usually addressed fast execution, security enhancements, and implementation of some HLLs abstraction. However, the main effort was always aimed to increase the performance. In the past, the limiting factor was the amount of resources (e.g., transistors) that could be used on a chip. Today's integration has overcome this limit. In this paper, we present memory hierarchy based on an enhanced segmentation model that provides support for fine-grained memory protection, data structures of high level programming languages, and GC. The memory sub-system was designed for fast execution and we designed special caches to achieve this goal. In following sections we describe the memory model and caches used for descriptors and local variables.