MIPS: A microprocessor architecture

Authors:
John Hennessy;Norman Jouppi;Steven Przybylski;Christopher Rowen;Thomas Gross;Forest Baskett;John Gill
Affiliations:
Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University;Departments of Electrical Engineering and Computer Science, Stanford University
Venue:
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Year:
1982

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Fundamenta Informaticae

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Abstract

MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.