Performance evaluation of a commercial cache-coherent shared memory multiprocessor

Authors:
Rajeev Jog;Philip L. Vitale;James R. Callister
Affiliations:
Hardware Systems Peformance, Hewlett Packard Company, 19447 Pruneridge Avenue, Cupertino, CA;Hardware Systems Peformance, Hewlett Packard Company, 19447 Pruneridge Avenue, Cupertino, CA;Hardware Systems Peformance, Hewlett Packard Company, 19447 Pruneridge Avenue, Cupertino, CA
Venue:
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Year:
1990

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Abstract

This paper describes an approximate Mean Value Analysis (MVA) model developed to project the performance of a small-scale shared-memory commercial symmetric multiprocessor system. The system, based on Hewlett Packard Precision Architecture processors, supports multiple active user processes and multiple execution threads within the operating system.Using detailed timing for hardware delays, a customized approximate closed queueing model is developed for the multiprocessor system. The model evaluates delays due to bus and memory contention, and cache interference. It predicts bus bandwidth requirements and utilizations for the bus and memory controllers. An extension to handle I/O traffic is outlined.Applications are profiled on the basis of execution traces on uniprocessor systems to provide inputs parameters for the model. Performance effects of various detailed architectural tradeoffs (memory interleaving, lower memory latencies) are examined. The sensitivity of overall system performance to various parameters is explored. Preliminary measurements of uniprocessor systems are compared against the model predictions. A prototype multiprocessor system is under development. We intend to validate the modeling results against measurements.