Introduction to algorithms
Bit Permutation Instructions for Accelerating Software Cryptography
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Notes on merging networks (Prelimiary Version)
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Fast Subword Permutation Instructions Using Omega and Flip Network Stages
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Bit permutation instructions: architecture, implementation, and cryptographic properties
Bit permutation instructions: architecture, implementation, and cryptographic properties
Digital Circuit Optimization via Geometric Programming
Operations Research
Exploring the design space of programmable regular expression matching accelerators
Journal of Systems Architecture: the EUROMICRO Journal
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Single or multibit subword permutations are useful in many multimedia and cryptographic applications. Several specialized instructions have been proposed to handle the required data rearrangements. In this paper, we examine the hardware implementation of the powerful permutation instruction group (GRP). The design of the proposed permutation unit is based on the functionality of sorting networks. Two variants of the sorter-based GRP unit are introduced and analyzed and their energy-delay behavior is investigated using static CMOS implementations in a 130-nm CMOS technology.