Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
Circuit techniques for dynamic variation tolerance
Proceedings of the 46th Annual Design Automation Conference
Thermal-aware voltage droop compensation for multi-core architectures
Proceedings of the 20th symposium on Great lakes symposium on VLSI
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
An event-guided approach to reducing voltage noise in processors
Proceedings of the Conference on Design, Automation and Test in Europe
Active management of timing guardband to save energy in POWER7
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
Proceedings of the 39th Annual International Symposium on Computer Architecture
DSN '12 Proceedings of the 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
Variation-tolerant OpenMP tasking on tightly-coupled processor clusters
Proceedings of the Conference on Design, Automation and Test in Europe
Compact degradation sensors for monitoring NBTI and oxide degradation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Aging-aware compiler-directed VLIW assignment for GPGPU architectures
Proceedings of the 50th Annual Design Automation Conference
ARGO: aging-aware GPGPU register file allocation
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Proceedings of the International Conference on Computer-Aided Design
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This paper proposes a new model of functional units for variation-induced timing errors due to PVT variations and device Aging (PVTA). The model takes into account PVTA parameter variations, clock frequency, and the physical details of Placed-and-Routed (P&R) functional units in 45nm TSMC analysis flow. Using this model and PVTA monitoring circuits, we propose Hierarchically Focused Guardbanding (HFG) as a method to adaptively mitigate PVTA variations. We demonstrate the effectiveness of HFG on GPU architecture at two granularities of observation and adaptation: (i) fine-grained instruction-level; and (ii) coarse-grained kernel-level. Using coarse-grained PVTA monitors with kernel-level adaptation, the throughput increases by 70% on average. By comparison, the instruction-by-instruction monitoring and adaptation enhances throughput by a factor of 1.8x-2.1x depending on the configuration of PVTA monitors and the type of instructions executed in the kernels.