Susceptibility of Commodity Systems and Software to Memory Soft Errors
IEEE Transactions on Computers
Area-efficient error protection for caches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Journal of Electronic Testing: Theory and Applications
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Flexible cache error protection using an ECC FIFO
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Partitioning techniques for partially protected caches in resource-constrained embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A framework for correction of multi-bit soft errors in L2 caches based on redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CPPC: correctable parity protected cache
Proceedings of the 38th annual international symposium on Computer architecture
Software encoded processing: building dependable systems with commodity hardware
SAFECOMP'07 Proceedings of the 26th international conference on Computer Safety, Reliability, and Security
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors
Proceedings of the 40th Annual International Symposium on Computer Architecture
Replicating tag entries for reliability enhancement in cache tag arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient L2 cache architecture using way tag information under write-through policy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
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The Itanium Processor is the first implementation of the Intel IA-64 architecture. Designed for the high-end server market segment, the processor is equipped with many advanced RAS (reliability, availability, and serviceability) features to maximize system reliability and availability.