Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The energy efficiency of IRAM architectures
Proceedings of the 24th annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
IEEE Micro
Energy-Delay Analysis for On-Chip Interconnect at the System Level
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
POWER4 system microarchitecture
IBM Journal of Research and Development
A Low Power Strategy for Future Mobile Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design of adaptive multiprocessor on chip systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Energy-efficient scheduling of a real-time task on DVFS-enabled multi-cores
Proceedings of the 2009 International Conference on Hybrid Information Technology
A robust seamless communication architecture for next-generation mobile terminals on multi-CPU SoCs
ACM Transactions on Embedded Computing Systems (TECS)
RCMP: a reconfigurable chip-multiprocessor architecture
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
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Power consumption has become an increasingly important factor in the field of computer architecture. It affects issues such as heat dissipation and packaging cost, which in turn affects the design and cost of a mobile terminal. Today, a lot of effort is put into the design of architectures and software implementation to increase performance. However, little is done on a system level to minimize power consumption, which is crucial in mobile systems.We propose an adaptive chip-multiprocessor (CMP) architecture, where the number of active processors is dynamically adjusted to the current workload need in order to save energy while preserving performance. The architecture is suitable in future mobile terminals where we anticipate a bursty and performance demanding workload.We have carried out an evaluation of the performance and power consumption of the proposed architecture using previously validated high-level simulation models. Our experiments show that orders of magnitude in power consumption can be saved compared to a conventional architecture to a negligable performance cost. The method used is complementary to other power saving techniques such as voltage and frequency scaling.