RCMP: a reconfigurable chip-multiprocessor architecture

Authors:
Raphael Fonte Boa;Dulcinéia Oliveira da Penha;Alexandre Marques Amaral;Márcio Oliveira Soares de Souza;Carlos Augusto P. da Silva Martins;Petr Yakovlevitch Ekel
Affiliations:
Pontifical Catholic University of Minas Gerais (Brazil);Pontifical Catholic University of Minas Gerais (Brazil);Pontifical Catholic University of Minas Gerais (Brazil);Pontifical Catholic University of Minas Gerais (Brazil);Pontifical Catholic University of Minas Gerais (Brazil);Pontifical Catholic University of Minas Gerais (Brazil)
Venue:
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
Year:
2006

Citing 6
Cited 1

CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit

Proceedings of the 27th annual international symposium on Computer architecture
Piranha: a scalable architecture based on single-chip multiprocessing

Proceedings of the 27th annual international symposium on Computer architecture
Reconfigurable computing: a survey of systems and software

ACM Computing Surveys (CSUR)
An adaptive chip-multiprocessor architecture for future mobile terminals

CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
A Single-Chip Multiprocessor

Computer
Scaling to the End of Silicon with EDGE Architectures

Computer

Parallel image segmentation in reconfigurable chip multiprocessors

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current parallel architectures are not optimized to all different kinds of applications since they can vary in requirements and resource needs. An ideal system to attend different applications should be able to fit their different characteristics and resource needs and to improve application performance. Our objective is to design and to develop a system architecture that can be reconfigured to fulfill many kinds of the application requirements and run with a reduced communication overhead. Our main goal is a new Reconfigurable Chip-MultiProcessor architecture that improves adaptability to have better performance, regardless of the application requirements. Our results and its analysis show that our architecture provides greater flexibility and scalability and still obtains performance gain over one multiprocessor architecture. Our main contribution is a Reconfigurable Chip-Multiprocessor architecture, composed of reconfigurable processing, storage and interconnection elements.