Limits of instruction-level parallelism
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
An elementary processor architecture with simultaneous instruction issuing from multiple threads
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Piranha: a scalable architecture based on single-chip multiprocessing
Proceedings of the 27th annual international symposium on Computer architecture
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
An adaptive chip-multiprocessor architecture for future mobile terminals
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
IEEE Design & Test
Performance Study of a Multithreaded Superscalar Microprocessor
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
IEEE Design & Test
Queue - Multiprocessors
Automated architecture synthesis for parallel programs on FPGA multiprocessor systems
Microprocessors & Microsystems
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
LPNMR '09 Proceedings of the 10th International Conference on Logic Programming and Nonmonotonic Reasoning
On-chip transactional memory system for FPGAs using TCC model
Proceedings of the 6th FPGAworld Conference
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
A reconfigurable multiprocessor architecture for a reliable face recognition implementation
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a design approach for adaptive multiprocessors on chip, in particular for FPGA devices. The approach consists of two steps in which the hardware infrastructure is first generated and then, the single processors, the peripherals as well as the custom hardware components are configured. In order to automatize the design process, to have the maximum freedom from the current design tools and hide their complexity to the designer, a platform independent tool was developed. As case study, we implemented the singular value decomposition (SVD) on the Xilinx ML310-Board with up to 8 processors. The results show considerable speed-up of the multiprocessor solutions produced toward the single processor ones.