Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Programming with transactional coherence and consistency (TCC)
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Characterization of TCC on Chip-Multiprocessors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Queue - Multiprocessors
Transactional Memory (Synthesis Lectures on Computer Architecture)
Transactional Memory (Synthesis Lectures on Computer Architecture)
ATLAS: a chip-multiprocessor with transactional memory support
Proceedings of the conference on Design, automation and test in Europe
Design of adaptive multiprocessor on chip systems
Proceedings of the 20th annual conference on Integrated circuits and systems design
SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Resource-bounded multicore emulation using Beefarm
Microprocessors & Microsystems
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The amount of processing elements in chip-multiprocessors is increasing continuous. Parallel programs use locks or mutexes to access shared resources. However, coarse-grained-locks are easy to write but limit the parallelization of the code, while fine-grained locks allow more parallel execution but often lead to deadlocks or other bugs, due to a more difficult program development. Hardware Transactional Memory allows an easement in parallel program development by providing a simplified concurrency management. The basic idea of transactional memory are atomic transactions, which offer a method for synchronization of processes without having the problems of synchronization methods like locks. In this paper a concept for adopting the TCC transactional memory model to Xilinx FPGAs using MicroBlaze soft-core processor is presented and first implementation details are given.