An adaptive chip-multiprocessor architecture for future mobile terminals
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Increasing power efficiency of multi-core network processors through data filtering
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Reducing energy and delay using efficient victim caches
Proceedings of the 2003 international symposium on Low power electronics and design
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Given today's deep submicron technologies, increasing clock rates, and ever-larger die sizes, interconnect plays an increasing role in determining the total chip area, delay, and power consumption. Thus, interconnects must be accounted for as early as possible during the design process. This paper presents a system level interconnect power and delay modeling method and applies it to a commercial chip that integrates a 16-bit DSP and a 32-bit RISC microcontroller. An architectural level simulator for the commercial chip has been enhanced to generate the bus activities for a set of signal processing benchmarks and some synthetic benchmarks. The power, delay and energy-delay measurements for all six top level buses of the chip are reported.