Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architecting ASIC libraries and flows in nanometer era
Proceedings of the 40th annual Design Automation Conference
An Efficient Methodology for Noise Characterization
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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In nanometer technologies, capacitive coupling between signal lines is increasing, thereby causing crosstalk-induced hazards. Crosstalk analysis and avoidance methodologies have evolved to tackle this problem through various stages of the design flow. To effectively avoid crosstalk and identify circuits failing due to crosstalk noise, certain noise related parameters have to be characterized for the cells in the technology library. Characterization of noise parameters such as noise immunity and propagation accounts for about 60% of the total ASIC library characterization cycle time, and hence becomes a bottleneck in the library creation process. In this paper we present a comprehensive methodology that enables noise characterization of nanometer libraries in reasonable time.