High-speed digital design: a handbook of black magic
High-speed digital design: a handbook of black magic
Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
Reducing the frequency gap between ASIC and custom designs: a custom perspective
Proceedings of the 38th annual Design Automation Conference
The iCOREtm 520 MHz synthesizable CPU core
Proceedings of the 39th annual Design Automation Conference
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work, a synthesizable architecture for serial high speed transceiver is presented, which can be implemented on register-transfer level (RTL) with standard hardware descriptionlanguages (HDL). The proposed implementation as a soft IP macro can be synthesized applying a semi-custom design flow, widely used in industry whenever possible.Generally, the implementation of high speed transceivers is a typical domain of a full custom design style because the timing critical parts are realized by dedicated transistor level design of the PLL/DLL based architectures. Compared to this method, the design productivity can be enhanced significantly, with the usage of this soft IP macro. With the presented implementation, data rates of about 1 GBit/s can be achieved. This is certainly less compared to full custom implementations. Nevertheless, this is an appealing solution for short design time and low cost design, if the achieved data rate is sufficient. In addition, current research showthat data rates above the mentioned result can be achieved.