Achieving 550 MHz in an ASIC methodology
Proceedings of the 38th annual Design Automation Conference
A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core
Proceedings of the conference on Design, automation and test in Europe - Volume 3
A study on factors influencing power consumption in multithreaded and multicore CPUs
WSEAS Transactions on Computers
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This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm2 in a 6-metal 0.18m CMOS process. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core [1].