NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Low-Cost Application-Aware DVFS for Multi-core Architecture
ICCIT '08 Proceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 02
Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
SCALCOM-EMBEDDEDCOM '09 Proceedings of the 2009 International Conference on Scalable Computing and Communications; Eighth International Conference on Embedded Computing
A feedback-based approach to DVFS in data-flow applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Distributed DVFS using rationally-related frequencies and discrete voltage levels
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As processor count in MPSoCs increases, the use of NoCs becomes relevant, if not mandatory. However, power and energy restrictions, especially in mobile applications, may render the design of NoC-based MPSoCs over-constrained. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved useful in several scenarios to save energy/power, but it presents scaling problems and slow response times. This work proposes a self-adaptable distributed dynamic frequency scaling (DFS) scheme for NoC-based MPSoCs. It takes into account the communication load and the utilization level of each processor to dynamically change its operating frequency. Frequency change decisions and clock generation are executed locally to each processor. Clock generation is simple, based on clock gating of a single global clock. The overhead of the scheme is minimum, the range of generated clocks is wide, and the response time is negligible. Experimental results with synthetic applications shows that the proposed scheme has an average execution time overhead below 7%, and may lead to considerable power and energy savings, since it allows an average reduction of 27% on the total number of executed instructions. Evaluating the proposed method with a real application, the execution time overhead reached 13%, while the total number of executed instructions was reduced by 64%.