A self-adaptable distributed DFS scheme for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Proceedings of the 48th Design Automation Conference
A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency Islands
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
Applying effective dynamic frequency scaling method in contactless smart card
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Writeback-aware bandwidth partitioning for multi-core systems with PCM
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
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As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2P, our proposed technique reduces 36.4% and 14.7% of ED2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.