The simulation and evaluation of dynamic voltage scaling algorithms
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IEEE Transactions on Computers
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Kalman Filtering and Neural Networks
Kalman Filtering and Neural Networks
Determining Asynchronous Acyclic Pipeline Execution Times
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Frame-based dynamic voltage and frequency scaling for a MPEG decoder
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-Level Energy Management for Periodic Real-Time Tasks
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
Microprocessors in the era of terascale integration
Proceedings of the conference on Design, automation and test in Europe
Feedback-controlled reliability-aware power management for real-time embedded systems
Proceedings of the 45th annual Design Automation Conference
Low-Cost Application-Aware DVFS for Multi-core Architecture
ICCIT '08 Proceedings of the 2008 Third International Conference on Convergence and Hybrid Information Technology - Volume 02
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
DELTA '10 Proceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Reliability aware power management for dual-processor real-time embedded systems
Proceedings of the 47th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic
Proceedings of the International Conference on Computer-Aided Design
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A processor's performance and power consumption are tied; an increased performance demands more power, and vice versa. An optimal tradeoff can only be achieved by an improved prediction of the task execution times, prior to an efficient scheduling. Moreover, since the processor's soft error rate is a function of its operating voltage, it is also linked to the performance-power trade-off. The situation is further complicated for the case of multicore architectures where the tasks are to be mapped on separate cores (processing elements). This paper proposes a joint State-Space model to achieve improved task execution time estimation, leading to better scheduling for optimizing the trade-off, particularly in the context of multicore soft real-time systems. It does not assume any `a priori' knowledge about the task graph or its properties, and is independent of the underlying architecture. It learns the system dynamics over time. The state-space solution is formulated using a recursive implementation of the online Monte Carlo Method. Having obtained the estimates of the execution times, they are compensated for the soft error according to a given soft error rate. At the beginning of each scheduling interval, the low power EDF scheduling decision is carried out to execute the tasks. The proposed method (SEAL) achieves 29% better energy savings compared to state-of-the-art, while the deadline misses are under 7% without the loss of system failure probability. The results obtained clearly show the advantage in terms of energy savings.