Trace theory and systolic computations
Volume I: Parallel architectures on PARLE: Parallel Architectures and Languages Europe
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
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