The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Newtonian arbiters cannot be proven correct
Formal Methods in System Design - Special issue on designing correct circuits
Localized verification of modular designs
Formal Methods in System Design
CMOS design of the tree arbiter element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
An Old-Fashioned Recipe for Real Time
Proceedings of the Real-Time: Theory in Practice, REX Workshop
Verifying a Self-Timed Divider
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Proving Newtonian arbiters Correct, almost surely
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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A merge element combines two, concurrent, handshake streams. For every request received from a client, a merge element may send a request to its parent, and for each acknowledgement received from its parent, the merge element may send an acknowledgement to a client. We show that that a merge-element can provide bounded time response if its parent also has bounded time response. We present two new implementations of a merge: one that uses an arbiter, and one that uses Schmitt triggers but no arbiters. Based on these designs, we explore a class of concurrent computations that can be performed in guaranteed bounded time, and we raise some new questions about what is possible in asynchronous design.