Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Can Redundancy and Masking Improve the Performance of Synchronizers?
IEEE Transactions on Computers
A Solution to a Special Case of the Synchronization Problem
IEEE Transactions on Computers
Digital engineering design: a modern approach
Digital engineering design: a modern approach
Modern Digital Design and Switching Theory
Modern Digital Design and Switching Theory
Modular Asynchronous Arbiter Insensitive to Metastability
IEEE Transactions on Computers
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Nowadays, metastability is becoming a serious problemin high-performance VLSI design, mainly due to the relatively-highprobability of error when a bistable circuit operates at highfrequencies. As far as we know, there is not any work publishedthat justifies and formally characterizes metastable behaviorin dynamic latches. With current technologies, dynamic latchesare widely used in high-performance VLSI circuits, mainly dueto their lower cost and higher operation speed than static latches.In this work, we demonstrate that dynamic memory cells presentan anomalous behavior referred to as metastable operation withcharacteristics similar to those of static latches. We performa suitable generalization of metastability to the dynamic case,applying it to a CMOS dynamic D-latch. A theoretical model willbe proposed, allowing the quantification of metastability, andit will be validated through electric simulation with HSPICE.After that, we have compared the metastable behavior of the dynamiclatch with its static counterpart, obtaining results about thecharacteristic parameters of metastability and the Mean TimeBetween Failures (MTBF) for both kinds of bistable circuits.These results have allowed us to conclude that, unlike metastabilitywindows in static latches, a clearly defined input interval existswhich produces an infinite resolution time. Regarding MTBF, thedynamic latch presents a very low MTBF value compared to thestatic latch. These results show that dynamic latches shouldnot be used in those circuits where the risk of asynchronismbetween clock and data signals is not negligible.