Noise tolerant low voltage XOR-XNOR for fast arithmetic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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Digital battery operated mobiles and implanted devices require maximum battery life. Extended battery life can be achieved by either operating at the lowest possible supply voltage or operating at the slowest possible speed. The advantages of Asynchronous circuits make it suitable for low power operation of the circuits. Asynchronous circuits stops computing when there is no change in the input there by eliminating the need for extra complexity of clock gating. The reduction in power also minimizes the efforts for the heat dissipation and cooling expenses. Low power and low energy techniques such as minimizing the number of transistors, voltage scaling are used. The implication of voltage scaling is a wide range of variation in the delay. Adders are representative of signal processing architectures. Asynchronous Adder circuits dissipate less power in applications where performance is non-limiting. Asynchronous adders can be implemented using static or dynamic circuits. Asynchronous dynamic adder circuits employ a single rail or dual rail logic or a combined logic. In this work Three Novel low power Asynchronous Full Adder circuits are proposed. The Circuits are implemented using cadence 90nm Technology and simulated using Spectre simulator. The delay achieved is 39ps, 40ps, 43ps as compared to 90ps for PTL Adder. The power delay product (PDP) obtained is 7.4e-18, 7.9e-18 as compared to PTL adder which is 5.4e-15. All the three proposed adder showed improvements in the Power, delay as well as PDP.