Computer arithmetic algorithms
Computer arithmetic algorithms
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
Multispeculative additive trees in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient and scalable OpenMP-based system-level design
Proceedings of the Conference on Design, Automation and Test in Europe
High performance reliable variable latency carry select addition
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration for high-level synthesis of multi-threaded applications
Journal of Systems Architecture: the EUROMICRO Journal
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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Existing architectures for speculative addition are all based on the assumption that operands have uniformly distributed bits, which is rarely verified in real applications. As a consequence, they may be disadvantageous for real-world workloads, although in principle faster than standard adders. To address this limitation, we introduce a new architecture based on an innovative technique for speculative global carry evaluation. The proposed architecture solves the main drawback of existing schemes and, evaluated on real-world benchmarks, it exhibits an interesting performance improvement with respect to both standard adders and alternative architectures for speculative addition.