IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Automatic synthesis of compressor trees: reevaluating large counters
Proceedings of the conference on Design, automation and test in Europe
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
Efficient synthesis of compressor trees on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving synthesis of compressor trees on FPGAs via integer linear programming
Proceedings of the conference on Design, automation and test in Europe
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Compressor tree synthesis on commercial high-performance FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Multi-operand adders usually consist of compression trees which reduce the number of operands per a bit to two, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3; 2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compression trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show its effectiveness against existing approaches at GPC level and on Altera's Stratix III.