IEEE Transactions on Computers
Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
IEEE Transactions on Computers
Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
IEEE Transactions on Computers
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Counting Responders in an Associative Memory
IEEE Transactions on Computers
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Recently, an algorithm has been developed for synthesizing generalized parallel counters (GPC's) with a network of smaller ones [11]. In this correspondence we obtain an upper bound q, for the number of levels q in the synthesis of GPC's. This upper bound generalizes and improves the values deduced by other authors in [13] and [14].