Optimization of synchronous circuits
Logic Synthesis and Verification
Automatic trace analysis for logic of constraints
Proceedings of the 40th annual Design Automation Conference
A predictive distributed congestion metric and its application to technology mapping
Proceedings of the 2004 international symposium on Physical design
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Sequential Circuits for Relational Analysis
ICSE '07 Proceedings of the 29th international conference on Software Engineering
Sequential circuits for program analysis
Proceedings of the twenty-second IEEE/ACM international conference on Automated software engineering
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We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of implementations that can replace a component of a larger design. The power of our approach is demonstrated by the fact that it generalizes immediately to arbitrary interconnection topologies, and to designs containing nondeterminism and fairness. We also describe control aspects of sequential synthesis and relate controller realizability to classical work on program synthesis and tree automata