Reencoding for cycle-time minimization under fixed encoding length

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers

Is redundancy necessary to reduce delay

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference

Sequential logic testing and verification

Sequential logic testing and verification

Sequential circuit delay optimization using global path delays

DAC '93 Proceedings of the 30th international Design Automation Conference

Efficient implementation of retiming

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits

Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms

Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines

FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design

Logic optimization and equivalence checking by implication analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Combinational and sequential logic optimization by redundancy addition and removal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems