IEEE Transactions on Computers
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
DELAY: an efficient tool for retiming with realistic delay modeling
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Placement driven retiming with a coupled edge timing model
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Efficient retiming under a general delay model
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Retiming with Interconnect and Gate Delay
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
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A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the synchronous circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed.