Proceedings of the 2001 international symposium on Physical design
Timing driven gate duplication in technology independent phase
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing driven gate duplication: complexity issues and algorithms
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Integration, the VLSI Journal
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning and placement for buildable QCA circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Replicated partitioning for undirected hypergraphs
Journal of Parallel and Distributed Computing
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Logic partitioning is an important area of very large scale integration computer aided design and there have been numerous approaches proposed. Logic replication, the duplication of logic in order to minimize communication between partitions, can be an effective component of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By adding new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 13.9% better results than the best existing replication techniques. When integrated into our already state-of-the-art (nonreplication) partitioner, we improve overall cutsizes by 38.8%, while requiring the duplication of at most 7% of the logic