Forensic engineering techniques for VLSI CAD tools
Proceedings of the 37th Annual Design Automation Conference
A Web-CAD methodology for IP-core analysis and simulation
Proceedings of the 37th Annual Design Automation Conference
Watermarking, tamper-proffing, and obfuscation: tools for software protection
IEEE Transactions on Software Engineering
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern VLSI designs; however, little has been done to protect them. Basically, given a problem Ρ and a solution Σ, we want to be able to determine whether Σ is obtained by a particular tool or algorithm.We propose two techniques that intentionally leave some trace or birthmark, which refers to certain easy detectable properties, in the design solutions to facilitate CAD tool tracing and protection. The pre-processing technique provides the ideal protection at the cost of losing control of solution's quality. The post-processing technique balances the level of protection and design quality.We conduct a case study on how to protect a timing-driven gate duplication algorithm. Experimental results on a large set of MCNC benchmarks confirm that the pre-processing technique results in a significant reduction (about 48%) of the optimization power of the tool, while the post-processing technique has almost no penalty (less than 2%) on the tool's performance.