A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a virtex-5 FPGA

  • Authors:

  • Malte Baesler;Sven-Ole Voigt;Thomas Teufel

  • Affiliations:

  • Institute for Reliable Computing, Hamburg University of Technology, Hamburg, Germany;Institute for Reliable Computing, Hamburg University of Technology, Hamburg, Germany;Institute for Reliable Computing, Hamburg University of Technology, Hamburg, Germany

  • Venue:
  • International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
  • Year:
  • 2010

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Abstract

Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.