Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations

Authors:
M. Vazquez;G. Sutter;G. Bioul;J. P. Deschamps
Affiliations:
-;-;-;-
Venue:
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Year:
2009

Citing 0
Cited 3

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Abstract

This paper presents FPGA implementations of add/subtract algorithms for 10麓s complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT麓s Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results have been compared with 2麓s complement binary implementations carried out on the same platform. Better time delays have been registered for decimal number within same range of operands.