An efficient tree architecture for modulo 2n + 1 multiplication
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
A Simplified Architecture for Modulo (2n + 1) Multiplication
IEEE Transactions on Computers
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
Efficient Diminished-1 Modulo 2^n+1 Multipliers
IEEE Transactions on Computers
Residue Number Systems: Theory and Implementation
Residue Number Systems: Theory and Implementation
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A high-speed, programmable, CSD coefficient FIR filter
IEEE Transactions on Consumer Electronics
Time-Multiplexed Multiple-Constant Multiplication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper presents a high-speed FIR channel filter using residue number system (RNS) whose frequency response can be reconfigured to adapt to a multitude of channel filtering specifications of a multi-standard software defined radio (SDR) receiver. The channel filters in the channelizer of an SDR extract multiple narrowband channels corresponding to different communication standards from the wideband input signal. The proposed architecture has been synthesized on TSMC 0.18 μm CMOS standard cell technology. Synthesis result shows that the proposed reconfigurable FIR channel filter, for a Digital Advanced Mobile Phone Systems (D-AMPS) example, offers speed improvement of 42% and AT complexity reduction of 26% over existing reconfigurable FIR method.