A low-voltage micropower asynchronous multiplier with shift-add multiplication approach
IEEE Transactions on Circuits and Systems Part I: Regular Papers
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A canonic-signed-digit coded genetic algorithm for designing finite impulse response digital filter
Digital Signal Processing
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Journal of Signal Processing Systems
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A new high-speed, programmable FIR filter is presented, which is a multiplierless filter with CSD encoding coefficients. We propose a new programmable CSD encoding structure to make CSD coefficients programmable. Compared with the conventional FIR structure with Booth multipliers, this coding structure improves the speed of filter and decreases the area. We design a 10-bits, 18-taps video luminance filter with the presented filter structure. The completed filter core occupies 6.8 × 6.8 mm of silicon area in 0.6 μm 2P2M CMOS technology, and its maximum work frequency is 100 MHz.