IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
IEEE Transactions on Computers
Low power showdown: comparison of five DSP platforms implementing an LPC speech codec
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Low power and high-speed implementation of fir filters for software defined radio receivers
IEEE Transactions on Wireless Communications
A high-speed, programmable, CSD coefficient FIR filter
IEEE Transactions on Consumer Electronics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient datapath merging for partially reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Time-Multiplexed Multiple-Constant Multiplication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software radio issues in cellular base stations
IEEE Journal on Selected Areas in Communications
Partial reconfigurable fir filtering system using distributed arithmetic
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Journal of Signal Processing Systems
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Reconfigurability and low complexity are the two key requirements of finite impulse response (FIR) filters employed in multistandard wireless communication systems. In this paper, two new reconfigurable architectures of low complexity FIR filters are proposed, namely constant shifts method and programmable shifts method. The proposed FIR filter architecture is capable of operating for different wordlength filter coefficients without any overhead in the hardware circuitry. We show that dynamically reconfigurable filters can be efficiently implemented by using common subexpression elimination algorithms. The proposed architectures have been implemented and tested on Virtex 2v3000ff1152-4 field-programmable gate array and synthesized on 0.18 µm complementary metal-oxide-semiconductor technology with a precision of 16 bits. Design examples show that the proposed architectures offer good area and power reductions and speed improvement compared to the best existing reconfigurable FIR filter implementations in the literature.