Xquasher: a tool for efficient computation of multiple linear expressions
Proceedings of the 46th Annual Design Automation Conference
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Journal of Signal Processing Systems
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This paper studies area-efficient arithmetic circuits to multiply a fixed-point input value selectively by one of several preset fixed-point constants. We present an algorithm that generates a class of solutions to this time-multiplexed multiple-constant multiplication problem by ldquofusingrdquo single-constant multiplication circuits for the required constants. Our evaluation compares our solution against a baseline implementation style that employs a full multiplier and a lookup table for the constants. The evaluation shows that we gain a significant area advantage, at the price of increased latency, for problem sizes (in terms of the number of constants) up to a threshold dependent on the bit-widths of the input and the constants. Our evaluation further shows that our solution is better suited for standard-cell application-specific integrated circuits than prior works on reconfigurable multiplier blocks.