Partial reconfigurable fir filtering system using distributed arithmetic

Authors:
Daniel Llamocca;Marios Pattichis;G. Alonzo Vera
Affiliations:
Electrical and Computer Engineering Department, The University of New Mexico, Albuquerque, NM;Electrical and Computer Engineering Department, The University of New Mexico, Albuquerque, NM;Microelectronics Research and Development Corporation, Albuquerque, NM
Venue:
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Year:
2010

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Abstract

Dynamic partial reconfiguration (DPR) allows us to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, we present two new DPR systems that allow for efficient implementations of 1D FIR filters on modern FPGA devices. To minimize the required partial reconfiguration region (PRR), both implementations are based on distributed arithmetic. For a smaller required PRR, the first system only allows changes to the filter coefficient values while keeping the rest of the architecture fixed. The second DPR system allows full FIR-filter reconfiguration while requiring a larger PR region. We investigate the proposed system performance in terms of the dynamic reconfiguration rates. At low reconfiguration rates, the DPR systems can maintain much higher throughputs. We also present an example that demonstrates that the system can maintain a throughput of 10 Mega-samples per second while fully reconfiguring about seventy times per second.