Partial reconfigurable fir filtering system using distributed arithmetic
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
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Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of Distributed Arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.