Proceedings of the 2008 Asia and South Pacific Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple constant multiplication through residue number system
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
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The most computationally intensive part of a wideband receiver is the channelizer. The computational complexity of linear phase finite impulse response (LPFIR) filters employed in the channelizer is dominated by the number of adders used in the implementation of the multipliers. In this paper, two methods are proposed to efficiently implement the channel filters in a wideband receiver based on common subexpression elimination (CSE). We exploit the fact that a significant amount of redundant multiplications exist in the filter-bank channelizer as it extracts multiple narrowband channels from the wideband signal. By forming three and four nonzero-bit super-subexpressions utilizing redundant identical shifts that exist between a two- nonzero-bit common subexpression (CS) and a third nonzero bit, or between two nonzero-bit CS, the number of adders to implement the channel filters can be reduced considerably. Furthermore, the complexity of the adders is analyzed and design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and the personal digital cellular (PDC) channelizers show that the proposed methods offer considerable reduction in the number of full adders when compared to conventional CSE methods.