On the design of modulo 2n-1 cubing units

Authors:
Evangelos Vassalos;Dimitris Bakalis
Affiliations:
University of Patras, Patras, Greece;University of Patras, Patras, Greece
Venue:
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Year:
2013

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Abstract

A hardware intensive operation that is frequently employed in several arithmetic processing applications is the computation of the third power (cube) of an operand. Residue Number System can be used in such applications. In this paper we present two methods for designing modulo 2n-1 cubing units that are based on reducing the size of the partial product matrix. The first method leads to faster circuits while the second one leads to smaller circuits for medium and large values of n. We also present minimized logic functions for efficiently designing modulo 2n-1 cubing units for small wordlengths (n