On the design of modulo 2n-1 cubing units
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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A new technique for computing the cube of an operand of any length is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is faster than previously proposed methods that compute the cube of an operand in parallel with the disadvantage that more counters are utilized to perform partial product reduction. Cubing circuits using the proposed techniques are implemented with several operand lengths and analyzed with regard to area consumption and latency. Results are shown for several designs in AMI C5N 0.6 ìm technology.