Area-time efficient multi-modulus adders and their applications

Authors:
H. T. Vergos;D. Bakalis
Affiliations:
Department of Computer Engineering and Informatics, University of Patras, 26500, Rio, Patras Greece;Department of Physics, University of Patras, 26500, Rio, Patras Greece
Venue:
Microprocessors & Microsystems
Year:
2012

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Abstract

Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are proposed for multi-modulus adders that support the most common moduli cases in RNS channels, that is, modulo 2^n-1, 2^n and 2^n+1. The proposed architectures use parallel prefix carry computation units composed of log"2n levels. The experimental results show that the resulting adders are significantly faster and/or smaller than the earlier proposals. Multi-modulus subtractors, multipliers and squarers that rely on the use of the proposed multi-modulus adders are also presented. The last two are shown experimentally to outperform the currently most efficient ones in area, delay and dynamic power dissipation terms.